1. Field
Example embodiments relate to a storage node, a semiconductor memory device and methods of operating and fabricating the same. Other example embodiments relate to a storage node, a phase change memory device and methods of operating and fabricating the same.
2. Description of the Related Art
A phase change random access memory (PRAM) may be one of non-volatile memory devices (e.g., a flash memory, a ferroelectric random access memory (FRAM) and/or a magnetic random access memory (MRAM)). A difference of a PRAM and other non-volatile memory devices may be a structure of a storage node. The storage node of a PRAM may include a phase change layer. A phase of the phase change layer may be changed from a crystal state to an amorphous state at a predetermined temperature, and from an amorphous state to a crystal state at a temperature lower than the predetermined temperature.
If a resistance of a phase change layer when a phase of the phase change layer is in an amorphous state is a first resistance, and a resistance of the phase change layer when a phase of the phase change layer is in a crystal state is a second resistance, the first resistance may be greater than the second resistance. A PRAM may be a memory device recording and reading bit data, using resistance characteristics of a phase change layer that a resistance of the phase change layer may be varied in accordance with a phase of the phase change layer as above.
FIG. 1 illustrates a conventional PRAM. Referring to FIG. 1, the conventional PRAM may include a transistor Tr, which may be composed of a source region S and a drain region D, and a gate G formed on a channel region C between the source and drain regions S and D, on a silicon substrate 7. The conventional PRAM may include a storage node 10 connected to either one of the two regions S and D of the transistor Tr, for example, the source region S. The storage node 10 may be connected to the source region S of the transistor Tr through a conductive plug 9. The storage node 10 may include a lower electrode 10a, a lower electrode contact layer 10b, a phase change layer 10c in which bit data may be recorded, and an upper electrode 10d, which may be sequentially stacked. The lower electrode 10a may also function as a pad layer providing a relatively wide area for the lower electrode contact layer 10b to be formed. The lower electrode contact layer 10b may contact a limited area below a bottom surface of the phase change layer 10c. 
FIGS. 2(a)-2(c) illustrate a method of operating the conventional PRAM. In FIGS. 2(a)-2(c), the storage node 10 may be illustrated for convenience. Referring to FIGS. 2(a)-2(c), it may be considered that the conventional PRAM is in a set state and that bit data 0 may be recorded when a phase of the phase change layer 10c is in a crystal state. A first phase change current I1 may be applied from the upper electrode 10d through the phase change layer 10c to the lower electrode 10a in the state that bit data 0 is recorded. The first phase change current I1 may be a current changing a phase of the portion contacting the lower electrode contact layer 10b of the phase change layer 10c to an amorphous state, and may be called a reset current. The first phase change current I1 may be a pulse current, and may be applied for several nanoseconds, and may have a greater value than that of a set current.
The first phase change current I1 may be focused on the lower electrode contact layer 10b being narrower in width than the phase change layer 10c. As a resistance of a portion A1 (hereinafter, referred to as a contact area) of the phase change layer 10c contacting the lower electrode contact layer 10b is increased, a temperature of the contact area A1 may increase up to a phase change temperature or higher while the first phase change current I1 is applied. A phase of the contact area A1 of the phase change layer 10c may be changed from a crystal state to an amorphous state. As such, it may be considered that the conventional PRAM is in a reset state and that data 1 may be recorded when the contact area A1 of the phase change layer 10c is in an amorphous state. A reference numeral h1 in FIG. 2(a) indicates a height of the first phase change current I1.
As shown in FIG. 2(b), when the contact area A1 of the phase change layer 10c is in an amorphous state, a second phase change current I2 may be applied to the storage node 10 in the same direction as that of the first phase change current I1. As the second phase change current I2 changes the phase of the contact area A1 of the phase change layer 10c from the amorphous state to the original crystal state, it may be called a set current. The second phase change current I2 may be a pulse current. An intensity of the second phase change current I2 may be lower than that of the first phase change current I1. An applying time of the second phase change current I2 may be equal to or longer than that of the first phase change current I1.
While the second phase change current I2 is applied to the storage node 10 as in FIG. 2(c), a resistance of the contact area A1 of the phase change layer 10c may be increased, and a temperature of the contact area A1 may be increased. Because the intensity of the second phase change current I2 is relatively low and its applying time is relatively long unlike the case that the first phase change current I1 is applied, a temperature of the contact area A1 may not increase up to the phase change temperature of the phase change layer 10c. As such, because the contact area A1 is heated for a relatively long time at a temperature lower than the phase change temperature of the phase change layer 10c, the contact area A1 may change from an amorphous state to a crystal state so that the phase change layer 10c may be entirely in a crystal state.
As described above, the resistance state of the phase change layer 10c in the conventional PRAM may be determined by the first phase change current I1, for example, a reset current, and the second phase change current I2, for example, a set current. The first phase change current I1 may be a current to change a phase of the phase change layer 10c from a crystal state to an amorphous state, for example, current to generate a heat melting the phase change layer 10c. On the contrary, the second phase change current I2 may be a current to generate a heat for changing a phase of the phase change layer 10c, which is in an amorphous state by the first phase change current I1, from an amorphous state to a crystal state, and may be lower in current intensity than the first phase change current I1.
In the conventional PRAM as described above, the first and second phase change currents I1 and I2 may be applied to the storage node 10 through the transistor Tr. An intensity of the first phase change current I1 as a reset current, and an intensity of the second phase change current I2 as a set current may all be lower than an intensity of a current allowable for the transistor Tr. As described above, because the first phase change current I1 of the first and second phase change currents I1 and I2 may be higher, it may be necessary to reduce a reset current not to limit an integration density of a future PRAM. As ways of reducing the reset current of the conventional PRAM as described above, there have been proposed methods of reducing a width of the lower electrode contact layer 10b, a method of oxidizing the lower electrode contact layer 10b, and a method of employing a higher resistance TiAlN layer as the lower electrode contact layer 10b. 
The methods may provide an effect of reducing the reset current because the lower electrode contact layer 10b may generate joule heat. Because the methods also increase the set resistance, a production yield and a reliability of the PRAM may be deteriorated.